Perimeter matrix ball grid array circuit package with a populated center

ABSTRACT

A ball grid array (BGA) integrated circuit package which has an outer two-dimensional array of solder balls and a center two-dimensional array of solder balls located on a bottom surface of a package substrate. The solder balls are typically reflowed to mount the package to a printed circuit board. Mounted to an opposite surface of the substrate is an integrated circuit that is electrically coupled to the solder balls by internal routing within the package. The outer array of solder balls are located the dimensional profile of the integrated circuit to reduce solder stresses induced by the differential thermal expansion between the integrated circuit and the substrate. The center solder balls are typically routed directly to ground and power pads of the package to provide a direct thermal and electrical path from the integrated circuit to the printed circuit board.

This is a Continuation Application of prior Application Ser. No. 08/959,546 filed Oct. 24, 1997 now U.S. Pat. No. 5,894,410 which is a Continuation application of prior application Ser. No. 08/623,355 filed Mar. 28, 1996 now abandoned entitled PERIMETER MATRIX BALL ARRAY CIRCUIT PACKAGE WITH A POPULATED CENTER.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an integrated circuit package.

2. Description of Related Art

Integrated circuits are typically mounted to a package that is soldered to a printed circuit board. One such type of integrated circuit package is a ball grid array (“BGA”) package. BGA packages have a plurality of solder balls located on a bottom external surface of a package substrate. The solder balls are reflowed to attach the package to the printed circuit board. The integrated circuit is mounted to a top surface of the package substrate, and electrically coupled to the solder balls by internal routing within the package.

FIG. 1 shows a solder ball array of a prior art BGA package 2. The solder balls 4 are arranged in a two-dimensional pattern across the bottom surface of the package. The integrated circuit 6 is centrally located on the opposite side of the package 2. The package 2 is typically constructed from a material which has a coefficient of thermal expansion that is different than the thermal expansion coefficient of the integrated circuit. It has been found that the differential thermal expansion between the integrated circuit and the package will induce temperature related stresses that fail solder joints in an area which corresponds to the outer edges of the circuit die.

FIG. 2 shows a BGA package 2 of the prior art which has an outer two dimensional array of solder balls 4. The solder balls 4 are located away from the package area that is beneath the integrated circuit 6. Locating the solder balls 4 away from the integrated circuit 6 reduces the thermal stresses on the solder joints created by the differential expansion between the package and the integrated circuit. Although effective in reducing solder failure the outer array pattern limits the input/output (I/O) of the package. Additionally, the integrated circuit generates heat which conducts through the solder balls and into the printed circuit board. Locating the solder balls at the outer perimeter of the package increases the thermal path through the package substrate. The longer path increases the thermal impedance of the package and the junction temperature of the integrated circuit. It would be desirable provide a BGA package that has a longer product life, lower thermal impedance and higher I/O than BGA packages of the prior art.

SUMMARY OF THE INVENTION

The present invention is a ball grid array (“BGA”) integrated circuit package which has an outer two-dimensional array of solder balls and a center two-dimensional array of solder balls located on a bottom surface of a package substrate. The solder balls are typically reflowed to mount the package to a printed circuit board. Mounted to an opposite surface of the substrate is an integrated circuit that is electrically coupled to the solder balls by internal routing within the package. The outer array of solder balls are located outside the dimensional profile of the integrated circuit to reduce solder stresses induced by the differential thermal expansion between the integrated circuit and the substrate. The center solder balls are typically routed directly to ground and power pads of the package to provide a direct thermal and electrical path from the integrated circuit to the printed circuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, wherein:

FIG. 1 is a bottom view of a ball grid array integrated circuit package of the prior art;

FIG. 2 is a bottom view of a ball grid array integrated circuit package of the prior art;

FIG. 3 is a side cross-sectional view of a ball grid array package of the present invention;

FIG. 4 is a bottom view of the package shown in FIG. 3;

FIG. 5 is a bottom view of an alternate ball grid array package.

DETAILED DESCRIPTION OF THE INVENTION

Referring to the drawings more particularly by reference numbers, FIGS. 3 and 4 shows a ball grid array (“BGA”) integrated circuit package 10 of the present invention. The package 10 includes a substrate 12 that has a top surface 14 and an opposite bottom surface 16. Mounted to the top surface 14 of the substrate 12 is an integrated circuit 16. The integrated circuit 18 is typically a microprocessor. Although a microprocessor is described, it is to be understood that the package 10 may contain any electrical device(s).

The top surface 14 of the substrate 12 has a plurality of bond pads 20 and a ground bus 22. The substrate 12 may also have a separate power bus 23 concentrically located about the integrated circuit 18 and ground pad 22. The integrated circuit 18 is coupled to the bond pads 20 and busses 22 and 23 by bond wires 24. The integrated circuit 16 is typically enclosed by an encapsulant 26. Although bond wires 24 are shown and described, the integrated circuit 18 can be mounted and coupled to the substrate with solder balls located on the bottom surface of the circuit die in a package and process commonly referred to as “C4” or “flip chip” packaging.

The bottom surface 16 of the substrate 12 has a plurality of contact pads 28. The contact pads 28 are coupled to the bond pads 20 and busses 22 and 23 by vias 30 and internal routing 32 within the substrate 12. The substrate can be constructed with conventional printed circuit board, or co-fired ceramic, packaging processes known in the art.

A plurality of solder balls 34 are attached to the contact pads 28 with known ball grid array processes. The solder balls 34 are typically reflowed to attach the package 10 to a printed circuit board (not shown).

The contact pads 28 are arranged in an outer two-dimensional array 36 and a center two-dimensional array 38. Each array contains a plurality of contact pads 28 that are separated from each other by a number of dielectric spaces 40. The outer array 36 is separated from the center array 38 by a dielectric area 42. The outer array 36 is preferably located outside of the outer dimensional profile of the integrated circuit 18. In this manner the solder joints of the outer array 36 are not subjected to stresses created by the difference in the coefficient of thermal expansion of the integrated circuit 18 and the expansion coefficient of the substrate 12. The center array 38 is located near the origin of the integrated circuit 16 in an area that does not undergo as much thermal expansion as the outer edges of the circuit die. Therefore the solder stresses created by the differential thermal expansion is minimal in the area of the center array 38. The separated arrays provide a pattern that minimizes the stresses on the solder joints.

The outer array 36 is typically coupled to the signal lines of the integrated circuit 16. The center array 38 is preferably coupled to the ground bus 20 and power bus 23 of the substrate 12. The vias 30 that couple the busses 22 and 23 to the center contact pads 38 provide a direct thermal path through the substrate. The direct path lowers the thermal impedance of the package 10 and the junction temperature of the integrated circuit 18. Additionally, the short electrical path lowers the self-inductance and reduces the switching noise of the integrated circuit 18.

In the preferred embodiment, the package 10 contains 292 contact pads 28 on a 27 by 27 millimeter (mm) wide substrate 12, or 352 contact pads 28 on a 35 by 35 mm substrate 12. The dielectric space 40 between the contact pads 28 is typically 1.27 mm. The package 10 typically has a height of approximately 2.5 mm.

The package 10 is assembled by attaching the solder balls 34 to the contact pads 28. The integrated circuit 18 is mounted and coupled to the substrate 12. The integrated circuit 18 is then enclosed by the encapsulant 26. The BGA package 10 is typically shipped to an end user that mounts the package 10 to a printed circuit board by reflowing the solder balls 34.

FIG. 5 shows an alternate embodiment of a package 10′ which has five or six rows of contact pads 28 in the outer array 36′ of the substrate 12′. The additional pads 28 increase the input/output (I/O) of the package 10. The outer array 36′ is preferably outside the outer dimensional profile of the integrated circuit 18 to minimize the stresses on the solder joints. The package 10′ may provide 324 contact pads 28 on a 27 by 27 mm substrate 10. The longer rows of the package 60 provide the approximate I/O of a 35 by 35 mm package, within the footprint of a 27 by 27 mm package.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art. 

What is claimed is:
 1. A semiconductor package, comprising: a substrate that includes a top surface and an exposed external opposite surface including a first, inner region, a second, outer region around the inner region, and a third region that separates the first and second regions; and a plurality of contacts including a first plurality of contacts and a second plurality of contacts, said first plurality of contacts located in a four-by-four matrix in the first region, and said second plurality of contacts located in the second region such that a smallest distance between adjacent contacts in both the first and second regions are smaller than a distance between the first and second regions, wherein the third region does not have any contacts located therein.
 2. The semiconductor package of claim 1, wherein the smallest distance between adjacent contacts in the first region is equal to the smallest distance between adjacent contacts in the second region.
 3. The semiconductor package of claim 1, wherein the plurality of contacts comprises a plurality of contact pads.
 4. The semiconductor package of claim 3 further comprising a plurality of solder balls attached to said contact pads of said first and second plurality of contacts.
 5. The semiconductor package of claim 1 wherein each of the second plurality of contacts is contained within a dimensional profile of an integrated circuit coupled to the top surface of the substrate.
 6. The semiconductor package of claim 1 wherein said top surface of said substrate has a plurality of bond pads.
 7. The semiconductor package of claim 6 wherein said top surface of said substrate has a ground bus that is connected to said second plurality of contacts by a plurality of vias that extend through said substrate.
 8. The semiconductor package of claim 6 wherein said top surface of said substrate has a power bus that is connected to said second plurality of contacts by a plurality of vias that extend through said substrate.
 9. The semiconductor package of claim 1 wherein said first plurality of contacts comprises at least five rows of contacts.
 10. A semiconductor package, comprising: a substrate that includes a top surface having a plurality of bond pads, and an exposed external opposite surface including an inner region, an outer region, and a middle region that separates the inner and outer regions; a plurality of contacts including a first plurality of contacts and a second plurality of contacts, said first plurality of contacts located in the outer region, and said second plurality of contacts located in the inner region such that the smallest distances between adjacent contacts in the inner and outer regions are smaller than a distance between the inner and outer regions, wherein the middle region is free of contacts; and an integrated circuit that is mounted to said top surface of said substrate and electrically coupled to said plurality of bond pads, wherein said first and second plurality of contacts are located respectively outside and inside a dimensional profile of said integrated circuit.
 11. The semiconductor package of claim 10, wherein the distances between adjacent contacts in the inner region are equal to the distances between adjacent contacts in the outer region.
 12. The semiconductor package of claim 10 further comprising a plurality of electrically conductive members attached to said plurality of contacts of said first and second plurality of contacts.
 13. The semiconductor package of claim 10 wherein said top surface of said substrate has a ground bus that is coupled to said integrated circuit and connected to said second plurality of contacts by a plurality of vias that extend through said substrate.
 14. The semiconductor package of claim 10 wherein said top surface of said substrate has a power bus that is coupled to said integrated circuit and connected to said second plurality of contacts by a plurality of vias that extend through said substrate.
 15. The semiconductor package of claim 10 further comprising an encapsulant enclosing said integrated circuit.
 16. An integrated circuit package for an integrated circuit which has a dimensional profile, comprising: a substrate that includes a top surface, and an exposed external opposite surface defined by a first region that is substantially equal to the dimensional profile of the integrated circuit, a second region, and a third region that separates the first and second regions; and a plurality of contacts including a first plurality of contacts and a second plurality of contacts, said first plurality of contacts located within the second region, and said second plurality of contacts located in the first region such that a first smallest distance between adjacent contacts in the first region is smaller than a second smallest distance between the first and second regions, said third region being a contact free region.
 17. The integrated circuit package of claim 16, wherein a distance between adjacent contacts in first region is the same as the distance between adjacent contacts in the second region.
 18. The integrated circuit package of claim 16 further comprising a plurality of solder balls attached to said plurality of contacts.
 19. The integrated circuit package of claim 16 wherein said top surface of said substrate has a ground bus that is connected to said second plurality of contacts by a plurality of vias that extend through said substrate.
 20. The integrated circuit package of claim 16 wherein said top surface of said substrate has a power bus that is connected to said second plurality of contacts by a plurality of vias that extend through said substrate.
 21. A semiconductor package, comprising: a substrate which has a top surface and an exposed external bottom surface, said external bottom surface having a plurality of contact pads, said plurality of contact pads consisting only of: an outer array of contact pads, each of said contact pads separated from each other by a first distance; a center array of contact pads, arranged in a four-by-four array, each of said contact pads separated by a second distance, said center array of contact pads being separated from said outer array of contact pads by a third distance which is larger than said first and second distances; and a plurality of conductive contacts attached to said contact pads of said substrate.
 22. The semiconductor package of claim 21 wherein said outer array of contact pads is located outside an outer dimensional profile of an integrated circuit coupled to the top surface of said substrate.
 23. The semiconductor package of claim 21 wherein said center array of contact pads is located inside the outer dimensional profile of an integrated circuit coupled to the top surface of said substrate.
 24. The semiconductor package of claim 21 wherein said outer array of contact pads is located outside an outer dimensional profile of an integrated circuit coupled to the top surface of said substrate, and wherein said center array of contact pads is located inside the outer dimensional profile of said integrated circuit.
 25. The semiconductor package of claim 21 wherein a distance between adjacent contact pads in said outer array is the same as the distance between adjacent contact pads in said center array.
 26. The semiconductor package of claim 21 wherein the smallest distance between adjacent contact pads in the outer array is smaller than the distance between the outer array of contact pads and the center array of contact pads.
 27. The semiconductor package of claim 21 wherein the top surface of said substrate has a ground bus that is connected to said center array of contact pads by a plurality of vias that extend through said substrate.
 28. The semiconductor package of claim 21 wherein the conductive contacts are solder balls.
 29. A semiconductor package, comprising: a substrate that includes a top surface having a bus and an exposed external opposite surface including a first, inner region, a second, outer region around the inner region, and a third region that separates the first and second regions; a plurality of contacts including a first plurality of contacts and a second plurality of contacts, said first plurality of contacts located in a four-by-four matrix in the first region, and said second plurality of contacts located in the second region such that a smallest distance between adjacent contacts in both the first and second regions are smaller than a distance between the first and second regions, wherein the third region does not have any contacts located therein; and a plurality of via interconnecting the first bus with a plurality of the first contacts.
 30. The semiconductor package of claim 29 wherein the top surface has a second bus, further comprising a plurality of vias interconnecting the second bus with a plurality of the second contacts. 